Blog: CS302 All current solved Qs by ash

• Draw the truth table for the Boolean expression ABC’+C’D+ABD’+A’B’D

A	B	C	D	ABC’	C’D	ABD’	A’B’D	ABC’+C’D+ABD’+A’B’D
0	0	0	0	0	0	0	0	0
0	0	0	1	0	1	0	1	1
0	0	1	0	0	0	0	0	0
0	0	1	1	0	0	0	1	1
0	1	0	0	0	0	0	0	0
0	1	0	1	0	1	0	1	1
0	1	1	0	0	0	0	0	0
0	1	1	1	0	0	0	0	0
1	0	0	0	0	0	0	0	0
1	0	0	1	0	1	0	0	1
1	0	1	0	0	0	0	0	0
1	0	1	1	0	0	0	0	0
1	1	0	0	1	0	1	0	1
1	1	0	1	1	1	0	0	1
1	1	1	0	0	0	1	0	1
1	1	1	1	0	0	0	0	0

• Convert the following decimal numbers into binary form using Sum-of-Weights method:

     a) 58  

Sum term	Binary number	Highest weight
58	100000	32
26	010000	16
10	001000	8
2	000010	2

b) 82

Sum term	Binary number	Highest weight
82	1000000	64
18	010000	16
2	0000010	2
0

• How BCD to 7-Segment Decoder is different from binary decoders?

Binary decodes is the simplest and most commonly used Decoders are the n-to-2ⁿ Decoders. These Decoders have n inputs and 2ⁿ outputs each, n-bit input selects 1 out of 2ⁿ output code.
On the other hand BCD to 7-Segmnet Decoder is a specific type of decoder that is used to convert a 4-bit BCD Code to a 7-Segment Code. The BCD to 7-Segment Decoder unlike the Binary Decoders activates multiple but unique set of outputs for each 4-bit BCD input combination.

• Give two types of high-density memory.

ROMS, EPROM, flash and PROMs are high density memories.

• Give three types of non-volatile memory.

ROMS, EPROM, EEPROM and flash are non-volatile memories.

• Draw the circuit diagram of Flash A/D Converter.

• Draw the state diagram of a 3-bit up-down counter. Use an external input X; when X sets to logic 1, the counter counts downward otherwise counts upward.

• What is the difference between following two statements X: = D and Y = D, and give the reason why do we use dot extension “.CLK” (e.g.  X.CLK = Clock) with logical declaration statements?

The first logical declaration statement indicates that X will be assigned the value of D on the
Clock transition and will hold the value until the next clock transition. The second logical
Declaration indicates that output Y is equal to input D.
The dot extension ‘.CLK’ is used to indicate that the register device is a clocked flip-flop. A
statement using the dot extension must accompany a logical declaration statement.
X := D; X.CLK = Clock;

• What is meant by Monotonicity of D/A convertors?

The output of the D/A converter should give an increasing analogue voltage output when the binary input is varied between its minimum and maximum values.

• What is meant by Non-Monotonicity of Digital to Analog converter? 

If the D/A converter outputs a lower voltage than its preceding output voltage the converter is said to exhibit non-monotonic behavior.

• Difference between Johnson and ring counter?

The Ring Counter is similar to the Johnson counter, except that the Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. All the flip-flops of the counter are cleared to logic low except for the first flip-flop which is preset to logic high.

• What is memory expansion process?

Computer and Digital systems have the capability to allow RAM memory to be expanded as the needed arises by inserting extra memory in dedicated memory sockets on the computer motherboard.

• Explain erase operation in context of FLASH Memory. (2)

During the erase operation charge is removed from the memory cell. A sufficiently large positive voltage is applied at the source with respect to the control gate. The voltage applied across the control gate and source is opposite to the voltage applied during programming. If charges are present on the gate, the positive voltage supply at the source attracts the electrons depleting the gate. A FLASH memory is erased prior to programming

• Explain state assignment process. (2)

Each state in a sequential circuit is identified by a unique combination of binary bits. Unless the output of the sequential is directly taken from the flip-flop outputs such as counters, the states can be selected to allow minimum bit changes when changing from one state to the other. Keeping the bits changes to minimum when changing from one state to the next, results in simpler combinational circuits that determine the next state

• How many bytes will be in 16K × 8 memory?

A 16 K x 8 memory, stores 16K bytes or 16 x 1024 = 16384 bytes or 131072 bits.

• What are the three operations of FLASH MEMORY?

FLASH Memory operations are classified into

•Programming Operation

• Read Operation

• Erase Operation

• Draw the function table of 8-t0-3 encoder

• Explain rotate Right Operation of shift register with the help of diagram. (3)

The serial output of the register is connected to the serial input of the register. By applying clock pulses data is shifted right. The data shifted out of the serial out pin at the right hand side is re-circulated back into the shift register input at the left hand side. Thus the data is rotated right within the register

• Define “excitation inputs”.

The inputs to the memory which allow the memory to change its state on a clock transition are known as excitation inputs or excitation variables.

• Differentiate between “MEMORY CAPACITY” & “MEMORY DENSITY”. (5)]

Each memory array has a maximum capacity to store information in the form of bits. Memory density on the other hand specifies the number of bits stored per unit area. More the number of bits stored in a unit area more dense the memory, that is, more bits are stored in less space. The capacity and the density of a memory are determined by the total number of cells implemented in a unit area.

• How can calculate the frequency of an unknown signal? 

The frequency of the unknown signal can be calculated by counting the number of clock pulses of the unknown signal and dividing the count number by the time interval in which the clock pulses are counted.

• Some of the counters (e.g. 74HC163) are called pre-set counters. why? 

(74HC163) are called pre-set counters because A counter set in advance to stop or produce output once a specific count has been reached

• Explain the implementation of First In First Out (FIFO) Memory by using RAM. 

Shift register based FIFO memory is used in digital systems designed for specific applications where small sized buffers are used to allow transfer of data between two devices operating at different data rates. Such digital systems either have no RAM or very small RAM for storing variables. Computers implement FIFO memory by reserving a part of their RAM memory for use as buffers. The Keyboard buffer for example is implemented by reserving a part of the RAM. When RAM is used as FIFO memory, two registers are used to point to the FIFO Buffer Out and Buffer In respectively. The two registers hold the addresses of the locations of the Buffer Out and Buffer In respectively, which are updated as new data is written into the buffer and previous data is read out from the FIFO buffer. Implementation of the FIFO buffer in RAM is usually takes the form of a circular buffer.

• A 4-bit serial in/parallel out register contains the value “0100”, how many clock signals will be required to shift the complete data out of the register.

After four clock transitions the 4-bit register has 4-bits of data

• Divide the following binary number “1101” by the binary number “101”

• Name the single change which can be made to convert a combinational circuit to a sequential circuit? 

We have to combine combinational circuit and memory element to convert it into sequential circuit.

• Write down two functions of registers?

Registers can store data generated at the output of the ALU. The registers can also be used to exchange or copy data

• Explain FLASH Analogue-to-Digital converter. (5)

The Flash A/D converter is based on a resistor potential divider, where multiple resistors of identical value form a voltage divider. A reference voltage is applied at one end of the potential divider which divides the voltage equally across all the resistors. The input analogue voltage is applied at the non-inverting inputs of a set of Op-Amp based comparators. The inverting input of each comparator is connected to the resistive voltage divider which provides reference voltages for all the comparators. If the input voltage is larger than the reference voltage the output of the comparator is logic high otherwise it is logic low. The outputs of all the comparators are connected to the input of a priority encoder which converts the comparator outputs to a binary coded equivalent value.

• Convert the following caveman number system into decimal number system. (5)
  i) Ω↑∑

Ωx5²+↑x5¹+∑x5⁰= 3x5²+4x5¹+0x5⁰=3x25+4x5+0x1=95
ii) ↑∆∆∑

↑ x5³+∆ x5²+∆ x5¹+∑ x5⁰=4 x5³+1 x5²+1 x5¹+0 x5⁰=4 x125 + 1 x25 + 1 x5+ 0 x1 =500+25+5+0 =530

• Subtract these hex numbers.  

A):  (8416   -   2A16)   =5A00 

B):  (C316    -    B816).=B00

• Draw circuit diagram for flip-flop based static memory cell.

• Which gate is used in comparators?

Exclusive-OR is used as a comparator.

• What is the purpose of sign(s) bit in floating point for binary numbers?

The single Sign (S) bit represents the sign of the number (0=positive 1=negative)

•  Write down three characteristics of serial in / serial out 4-bit right shift register.

A basic four-bit shift register can be constructed using four D flip-flops, as shown below.  The operation of the circuit is as follows.  The register is first cleared, forcing all four outputs to zero.  The input data is then applied sequentially to the D input of the first flip-flop. During each clock pulse, one bit is transmitted from left to right

• How DRAMs are different from SRAMs? Write down the point of different ???

RAM is divided into two types, Static RAM which uses flip-flops as storage elements and Dynamic RAM which uses capacitors to store binary information.

• Convert them  binary to hexadecimal or hexadecimal to binary

(a)   11010000100

0110 1000 0100

   6        8        4

(b)        7      A       1         6

0111   1010   0001   0110

(c)    10001001

1000    1001

   8           9

(d)   001001111000

0010   0111    1000

   2          7          8

(e)   000101010111    

0001  0101  0111    

   1         5         7 

• What are the Analogue-to-Digital Converter Errors and explain these errors.

Analogue to Digital converters exhibit three different types of errors during their conversion operation. The three errors encountered during the conversion operation are the Missing Code, Incorrect Code and the Offset error.
1. Missing Code
In this error some code do not appear the missing code in the case of a Flash converter is due to the failure of a comparator which fails to provide an appropriate input to the Priority Encoder.
2. Incorrect Code
Incorrect Code at the output of the A/D converter is due to a particular bit stuck at some fixed logic value.
3. Offset Error
The offset error occurs when the binary output of the A/D converter represents a value which is greater than the actual analogue input signal value. The error is due to a fault in the comparator circuit. The offset error can be compensated by adjusting the output with respect to the amount of offset error.

• what is the reason of split up the memory in rows and columns also give the reason that why memory access gets slow as memory gets larger (5)

Large memories such as the 16 KB memory have row and column decoders that split the input address into a row address and a column address and activate a row and column select lines respectively. The row and column select lines select a location in the memory array. The memory is arranged in a two-dimensional manner instead of the linear address .The reason for adopting a row and column decoder to independently but simultaneously select a location by its unique row and column number is to speed up the decoding process. As the memories get larger the decoders that decode and select a unique memory location also become very large with large number of gates. Due to the increased level of gates of the decoding circuitry the delay in decoding the input address increases, thereby slowing the memory access.

• Draw the tri state buffer as a not gate. and show the high impedance by diagram (5)

• Draw the op-Amp as an inverting Amplifier. (3)

• Draw 2 to 4 decoder function table.

• Differentiate b\w synchronous and asynchronous RAM.

Synchronous RAM is very similar to the Asynchronous RAM, in terms of the memory array, the address decoders, read/write and enable inputs. In the Asynchronous memory the various input signals are asynchronous and are not tied to the clock, whereas in the Synchronous memory all the inputs are synchronized with respect to the clock and are latched into their various registers on an active clock pulse edge.

• Make block diagram of rotate left operation of a shift register and explain its working??

The serial output of the register is connected to the serial input of the register. By applying clock pulses data is shifted left. The data shifted out of the serial out pin at the left hand side is re-circulated back into the shift register input at the right hand side.

• Draw the block diagram of 4 bit BCD Adder.

• What is RAM stack? Which register store the address of top of the stack?

Shift Register based Stack implementation finds use in specialized digital systems. A practical way to implement the program stack which a program under execution uses to access variables is by means of the RAM memory. The stack is known as a RAM Stack. A special purpose register known as the ‘Stack Pointer Register’ stores the address of the top of the stack, a reserved area in the RAM memory

• Explain burst feature of synchronous SRAM with the help of example.

The Synchronous SRAM also has a Burst feature which allows the Synchronous SRAM to read or write up to four locations using a single address. When an external address is latched in by the Address register, the lower two bits of the address are connected to the Burst logic circuitry which internally increments the addresses at each clock transition producing four different addresses 00, 01, 10 and 11. For example, if an external base address of 37A0 H is stored in the Address Register, the Burst Logic circuitry produces addresses 37A0, 37A1, 37A2 and 37A3.

• In the statement: X   pin22    ISTYPE reg.buffer.  What is the meaning of the keyword reg.buffer.

The statement describes X output variable as an active-high Registered Mode.

• Tri-state buffer control input can be connected in four different ways? Name any three?

The tri-state buffer connecting the output of the OLMC circuit to the output pin is controlled through four different sources. The tri-state buffer control input can be connected in four different ways.
1. Connected to Vcc. The output is always enabled.
2. Connected to GND. The output is disabled and the output pin is configured as an input pin.
3. Connected to the external pin (11) which can be connected to Vcc or GND. The tri-state buffer is therefore controlled externally by applying an appropriate signal at the pin.
4. Connected to the output of one of the eight AND gates connected to the OLMC. Thus the tri-state buffer is controlled by a logical expression

• Write three guidelines for selection of state assignment?

The selection of State Assignment is based on the following guidelines.

• • Choose an initial coded state into which the state machine (sequential circuit) can easily be

forced to reset (000 or 111)

• • Minimize the State Variables that change on each transition
• • Maximize the number of state variables that don’t change in a group of related states
• • If there are unused states, then choose the best state variable combinations to achieve the

first three goals.

• General sequential circuit consists of memory element. How this memory element is implemented?

The memory element is made of a set of n flip-flops all connected to a a common clock. The n flip-flops store 2ⁿ states.

• Write down an advantage of state reduction process.

Due to state reduction we remove the duplicate states then the state diagram become very simple.

• Draw next-state table of an UP-Counter with help of J-K flip-flop. (5)

• define state reduction (2)

It is possible that two or more states are equivalent. Two states are considered equivalent if for the same set of inputs the states change to the same next state or equivalent next states and give identical outputs. If equivalent states exist then one of the equivalent states is removed. Reduction in the number of state results in fewer flip-flops and a simpler circuit.

• What will be the next step of designing a circuit, after we have drawn the state diagram?

Once the state diagram of the sequential circuit is defined, a Next-State Table is derived which lists each present state and the corresponding next state.

• What is the difference b/w counter and shift register?

A register can hold data, and it can be used for temporary storage or, in the case of an accumulator, it can participate in arithmetic or logical operations.
A counter is a special case of a register. Usually, it can only be loaded, stored, or incremented, or used for the stack or as the program counter.

• In asynchronous transmission, how the receiver gets to know that the data is going to be transmitted?

When the line is idle it is set to logic high, when a character is about to be transmitted the start bit sets the line to logic low. The logic low start bit is a signal for the receiver circuit to start receiving.

• How many address bits or required for a 2048 bit memory organized as a 256x8 memory ?

2ⁿ=2048  =>  2¹¹=2048  =>n=11

• A memory has 65536 unique locations. On how many bits (line0 will the address bus be composed?

2ⁿ=65536  =>  2¹⁶=65536  =>n=16

• Which is the normal mode of operation for a PROM?

PROM uses a fusible link to connect the output of the MOS transistors to the column line. The row lines are permanently connected the gates of the transistors. When the fuse is intact, logic high is seen on the column line when the corresponding cell is selected. When the fuse is blown the column line outputs a logic low.
  

• Suppose a 2 bit up down counter having states A,B,C,D,the counter counts upwards when X=1 and downwards when X=0 .write down IF THAN ELSE statements to  show how present states changes to next state and previous state?? 
• Suppose a 2 bit. Counter having states A, B, C, D write down GOTO statement to show how present state change to next state.
• What is the most appropriate logic gate to perform Boolean OR addition?
• What is a bit storage capacity of ROM with 512 * 8 organizations?
• Draw a complete test vector table for a 3 bit up/down counter using the following information;
   X is excitation input
   Clear input is zero the output cleared to( 000)
  When clear input is set to 1 counter functions normally
  Clean clock and X are inputs for up/down counter
• With context to flash memory, the row and column lines are connected to which terminals of MOS transistors.
• How many sets of input conditions produce a high (or 1) output in a five input OR gate.
• With context to flash memory, the row and column lines are connected to which terminals of MOS transistors.
• What will be the binary value of easy product then from which followings standards SOP expression is equal to 
• Which of the following is DIGITAL & which is ANALOG? (2)
  a) Pressure in a bike’s tire
  b) Temperature
  c) Speed of a car
  d) Number of students in a class