Blog: Explain the truth table and timing diagram of Gated S-R latch and Gated D latch in detail.

Explain the truth table and timing diagram of Gated S-R latch and Gated D latch in detail.
The logic symbol for the S-R flip-flop is shown here and its operation outlined in Table below.

Now we examine the output waveforms from the S-R flip-flop given the inputs. Assume that Q is HIGH initially.

The logic symbol for the D flip-flop is also shown below and its operation outlined in the Table. Notice that this flip-flop only has one input in addition to the clock called the D-input. Note that whatever is on the D-input when the trigger occurs is output at Q.

Notice that a D flip flop can be made from a S-R flip flop by ensuring that the S and R outputs are the complement of each other at all times.