CS302- Digital Logic Design
Assignment # 5
FALL 2010
Total Marks: 20
Due Date
Your assignment must be uploaded before or on 27th Jan 2011.
Upload Instructions
Please view the document related to assignment submission process provided to you by the Virtual University
Rules for Marking
Kindly note that your assignment will NOT be graded if:
§ It is submitted after due date
§ The file you uploaded does not open
§ The file you uploaded is copied from someone else
§ It is in the format other than .doc
Objective
This assignment has been designed to enable you to understand the concepts of:
§ Logic gates
§ Flip-flops
§ Shift Registers
Assignment
A 4-bit bidirectional shift register is shown in the figure below.
Initially, Q0 = Q1 = Q2 = Q3 = 0 and serial data-input line has 1.
Fill the table given below:
Clock Pulse |  RIGHT/LEFT | G1 | G2 | G3 | G4 | G5 | G6 | G7 | G8 | Q0 | Q1 | Q2 | Q3 |
1 | HIGH | ||||||||||||
2 | HIGH | ||||||||||||
3 | LOW | ||||||||||||
4 | LOW | ||||||||||||
5 | LOW | ||||||||||||
6 | LOW | ||||||||||||
7 | HIGH | ||||||||||||
8 | HIGH | ||||||||||||
9 | LOW | ||||||||||||
10 | LOW |
.........................
Design a 4-bit asynchronous down counter with truncated sequence that counts down a truncated sequence from 1111 to 0101. On reaching the count value 0100, the counter must preset to 1111.
Also draw its timing diagram.
Solution:
Timing Diagram:
When the counter values reaches 0100, it starts counting from 1111.
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